Electronic multiplying apparatus and circuitry therefor



United States Patent 1 1 3,544,780

[72] Inventor Pierre Rcfemlccs Cited A Lgg-lu-Roles, France UNITED STATES PATENTS 1 pp 624 3,2l9,808" 11/1965 Lee 235/194 5 ted 3 3,304,419 2/1967 l-luntley,Jr. m1 235/194 a en 3,393,307 7/1968 Courtenay et al. 235/194 [731 l WWW!" 1 3 437 836 4 1968 11 11 307 229 Courbevok cc u X 32] Priority March 21, 1966, March 13, 1967 Pnmary Emma-Eugene Boltz [33] an Assistant Examiner-Joseph F. Ruggiero [31] No 4 2 2 m 93 430 Attorneys-Dale A. Bauer, John L. Seymour and Bauer and Seymour ABSTRACT: An electric multiplier for producing an algebraic product A X B comprising (1) a device having a source of electrical energy, a PNP-type transistor and an NPN-type 1 v transistor capable of delivering on two output terminals voltages corresponding to A and A when a voltage representing [54] APPARATUSAND A is supplied to an input terminal and (2) a transistorized E 19 D I commutator circuit having two input terminals connected to 25 said output terminals, a signal input terminal connected to the [52] [1.8. CI 235/ 194, base electrodes of two transistors for receiving a voltage 307/229 representative of B and an output terminal for delivering a [51] In, (I L063 1/16 voltage representative of said product; and said multiplier cir- [50] Field Search 235/194, cuit in combination with a two-phase control motor and with magnetic memory means.

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IRVENTOR PIERRE JORGENSBN ELECTRONIC MULTIPLYING APPARATUS AND CIRCUITRY THEREFOR The present invention relates to electrical apparatus and more particularly to solid state conduction control circuitry adapted, among other things, for use in electronic calculators and the like.

An object of the present invention is to provide a novel scalar multiplier circuit.

Another object is to provide novel solid state electronic circuitry adapted for producing the algebraic product of two quantities representable by electrical values.

A further object is to provide a novel electronic scalar multiplier for producing an algebraic product of two numbers in strict fashion when one of the numbers is quantified'according to two or three values, such as, for example, positive without value and negative and in approximate fashion for those quantifications of a higher order. 2

Still another object of the invention is to provide'a novel phase demodulator embodying multiplier circuitry of the" above character.

Still another object of the invention is to provide an electronic multiplier circuit of the above character in novel combination with a magnetic memory device.

The basic multiplier circuit contemplated by the invention comprises a device embodying two transistors or comparable conduction control means capable of deliveringon two output electrodes voltages representative of the positive and .negative of a number A if a voltage representing the number is applied to an input terminal of the device. Connected to said device is a commutator circuit having an output terminal, a control terminal for receiving a signal indicative of a number B and'two input terminals connected to the output terminals of said device. The commutator circuitry is such that if B is positive, the commutator output is connected by a solid state switch to the commutator input electrode which receives a voltage representative of the number A, whereas if B is negative, the commutator output electrode is connected by a solid' state switch with the commutator input terminal thereof which receives a voltage signal representing the number --A. Finally, if B is without value, both input terminals of the commutator will be connected to each other and with the output terminal thereof. Thus, for the values of input signals A and B given in the following table, the commutator output voltage V will be- It will be noted that the sign of the voltage V corresponds to the product of the signs of the input signal voltages A and B.

The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.

In the drawings,

FIG. I is a circuit diagram illustrating one embodiment of the invention;

FIG. 2 is a duplicate of FIG. 1 wherein exemplary values of some of the components are indicated;

FIG. 3 is a circuit diagram showing a second embodiment;

FIG. 4 is a diagram illustrating the combination of the apparatus of FIGS. 1 or 2 with a two-phase control motor;

FIG. 5 is a graphic illustration of typical input and output voltages of apparatus embodying the invention;

FIG. 6 illustrates a phase demodulator embodying the circuitry ofFlG. l;

FIG. 7 is a diagrammatic plan view of a magnetic memory device;

FIG. 8 is an end elevation view of the device of FIG. 7 looking in the direction of the arrow VIII;

FIG. .9 is adiagrammatic detail view of a recording track and a reading her head therefor;

FIGS. 10A, 10B, l0C, l0D,- 10E, 10F and. 10G are respectively graphic representations of voltage plotted against time of a'reference signal that can be taken from the reading head ofFIG. 9, a signal representing the positive state, the product of those ,two signals, a signal representing the No Value state, the product of that signal and the referencesignal, a signal representing the negative state and the product of that signal and the reference signal;

FIG. 11 is a diagram showing memory device-reading heads in combination with circuitry shown in FIG. 1;

FIG. 12 is adiagram of circuitry adapted for recording signals on the memory track of the device of FIG. 7; and

FIG. 13is a duplicateof a portion of the diagram of-FIG. 12 wherein exemplary values of some of the components are indicated.

One embodiment of the present invention is illustrated in FIGS.. 1V and 2, by way of example, as including a twotransistor device-L comprising an NPN-type transistor T1 and aPNF'type transistor T2 which may be transistors known commercially as Texaslnstruments Company types 1.305 and L306. Each of said transistors has collector, emitter and base terminals or electrodes. Electrical energy is supplied to the transistors by a suitable source such as a 24-volt battery throughacircuit comprising conductors 1 and2. The voltage on conductor 1 may bedesignated Vb and that on conductor 2 may be zero or ground potential. Conductor l is connected to thecollector. terminal of transistor T1 and the emitter terminal of. transistor; T2 through a resistor R0 at a. junction D. Conductor 2 isconnected to the emitter terminal of transistor T1 through a resistor R1 and junction point F1 and to the collector terminal of transistor T2 through a resistor R2 and a junction point F2, said resistors being ofequal value. The base terminal of transistorTl is connected to-asignal input terminal A through-a resistor R3, and the base terminal of transistor T2 is connected at a junction point C, between resistors R4 and R5 which are connected in series between conductors 1 and 2. A terminal P- is also connected to conductor 1 between resistances (FIG. 2) or. other voltage dividing or distributing means 6. (FIG. 1). Corresponding resistors in FIG. 6 are designated R10 and R11. The supply voltages at points D, F1 and F2 may be designated V V and V respectively. Likewise, the voltage at point C, predetermined by the componentsR4 and R5 may be designated V The points F1 and F2 are output terminals of the device L and are connected in the embodiment of FIG. 1 to input terminals of a commutator circuit M. The latter comprises two solid statev conduction. control devices which in the form shown are an NPN-type transistor T3 and a PNP type transistor T4, each transistor having collector, emitter and base electrodes or terminals. The collector terminal of T3 is connected to terminal F1, and the emitter terminal of transistor T4 is connected to terminal F2. A signal input terminal B is connected to the base terminals of transistors T3 and T4 through resistors R6 and R7, respectively. The emitter terminal of. transistor T3 and the collector terminal of transistor T4 are connected through equal resistors r3 and r4 respectively, to a single commutator output terminal S.

In thefollowing description of the operation of the combined circuits L and M, it is assumed that resistance components thereof have the values indicated for corresponding components in FIG.v 2, or other values in the same proportion. In particular, R1. is equal to R2, R6. is equal to R7, and r3 is equal r4 and by reason of the PN junction at transistor T2, the voltage V at point D will be equal to the voltage V at point C, and by reason of the NP junction at transistor T1 the voltage V at terminal F1 is equal to the voltage V,, at input terminal A. Also, the intensity of the current i t traversing resistance R0 is equal to the sum of the current i1 and i2 traversing the resistors R1 and R2, respectively.

The constancy of the current i t, resulting from the fact that the ends of resistance R0 are at predetermined potentials V and V brings about the constancy of the sum of currents i1 i l T1 hence the constancy of the sum V V the value of which may be designated by 2V where V is the potential at point P. V and V are consequently equal to the sum and the difference, respectively, of V and V VF! VP VA Vim VP This sum and this difference are obtained by applying the voltage V between the point A and the point P of potential V If a voltage V is established between terminal B and point P, the voltage V, at output terminal S will have a value greater than V if the voltage V is positive, and a value less than V, if the voltage V, is negative. When the voltage V,, is positive, the potential of the base of transistor T3 is greater than the potential of its emitter electrode, and when voltage V is .negative, the potential of the base of transistor T4 is less than the potential of its collector electrode. When no voltage is applied at B, that is, when V is without value, transistors T3 and T4 are both blocked if V, is positive. In that case, the potential of the base electrode of transistor T3 will be lessthan the potential of its collector and emitterelectrodes, andthe potential of the base of transistor T4 will be greater than the potentials of its emitter and collector electrodes. Consequently, terminals S, B and P will all be at the same potential. If, on the'other hand, V is negative when'V is without value, transistors T3 and T4 become conductive and by reason of the equality of current limiting resistors r3 and r4, the potential of the terminal S is still at the potential level of the point P. From the foregoing, the following table may be formulated for the values of'voltages at points A, B and S, wherein the signs and sym-' bolize, respectively, a voltage greater than V a voltage equal and i2, equal respectively to ,,and

' to V and a voltage less than V B -000+- Vs .'.+0"-00o-0+ It will thus be seen. that the voltage V in each vertical column is the product of the signs of A and B in the same column, the module of this product being equal to at least the modules of A andB.

lna preferred embodiment, as shown in FIGS. 1 and 2, re-

2 R5 are given values proportional to and resistances R4 and R Iy.For example, R0 may have a value of l k when R4 has the same value and R5 has a value of 2 k as indicated in FIG. 2. Whenthe elements 6 are resistors with the values indicated in FIG. 2, the point P is brought to a potential Accordingly, the three potentials -g g values 0 and in the table above.

The embodiment of the invention illustrated in FIG. 3 is identical with FIG. 1, except that the two-transistor commutator M is replaced by apparatus Mcomprising two vibration emitters 3a and 3b connected in series between point C and conductor 2 with a center tap 5 connected to control terminal B. Vibration receivers 40 and 4b, the electrical characteristics of which vary under action of the vibrations of the cor responding vibrations of the corresponding vibration emitter, have the input terminals thereof connected respectively to terminals F1 and F2. The output electrodes or terminals of receivers 40 and 4b are connected to the common output terminal S by resistances rb and ra, respectively. Vibration emitters 3a and 3b may be discharge tubes, such as nonpolarized gaseous discharge tubes, Hertzian radiating oscillators or electric or electromagnetic vibrators. The corresponding receivers 4a and 4b may be photoelectric resistance, resistances, transistors havingbases equipped with antennae or carbon granule microphones.

The operation of the embodiment of FIG. 3 is as follows:

When receiver. 40 is rendered conductive by vibration emitter 3a, the potential V will be applied to output elecand 0, represent the ously energize both emitters 3a and 3b.

When one of the control voltages, for example, V is an alternating current voltage, the output voltage V,- which will also be alternating will be eitherin-phase or out-of-phase or null. (without value) in relation to V depending upon whether V is positive, negative or without value. In this case, the output voltage V may be used to control the operation and direction of of rotation of a two-phase electric motor, for

. example a step-by-step motor type U510 of the Societe de la Radiotechnique or an trated in FIG. 4.

The motor as illustrated by way of example comprises a rotor 7 which may be caused to rotate in either direction by two fixed windings 8 and 9 mounted with their axes 8a and 9a perpendicular to each other. The windings'are connected in series between terminals 10 and 11 and connected by a center tap to terminal P. If the terminals 10 and P are connected across a source (not shown) of alternating current voltage E, the rotor 7 will rotate in a forward direction, a reverse direction or stop, depending upon whether one applies between terminals 11 and P a voltage Ex (FIG. 5) out-ofasynchronous two-phase motor as illusphase by in relation to voltage E (curves 5a and 5b), a

voltage is Ex out-ofiphase by in relation to E (curve 50),

or no voltage (curve 5d), respectively. These voltage variations between terminals 11 and P may be obtained by inserting and 0, and control voltages b minimum values T K2 3 and minimum values and 0 the voltage E likewise having maximum and 0. sary, terminal 11 may be connected to output terminal S of the multiplier L,M through suitable amplifying means, such as a push-pull amplifier N embodying transistors T5 and T6 of type NPN and PNP.

As illustrated in the novel embodiment of FIG. 6, the voltages V and V may both be alternating current voltages. Voltage V V sinmt, having a maximum value V and a frequency to applied between terminal 22 and terminal P of a If desirable or necesmultiplier circuit L, M as well as to the ends of winding 21 of a selsyn rotor and to point B of the multiplier circuit through a resistor R8, generates in stator coil winding 20 connected between terminals P and A a voltage V, V C086 sinapt proportional to the cosin of the angle 0 and between the axes 20a and 21a of windings 20 and 21. On output terminal S one receives a voltage signal proportional to cosin0 to sin2wt allowing an average value proportional to cosin 6, this average value being obtained by employing a filter comprising a resistor R9 and a condenser 23. It will be noted that point P is,

F nected'with appropriate resistors R 10 and R 11 in the manner shown between the mass or ground and terminal G of potenu V tial V an alternating current voltage of maximum value for example, brought to a potential when it is connumbers are positive; the product is negative if the numbers have contrary signs, and it is valueless if either number is valueless. The distinction between these values may be made by a known comparison circuit of scalar values, such as that disclosed in French Pat. No. 1,478,391.

Additionally, the circuit embodying the invention may serve to take a predetermined fraction of a value or of a voltage, to inverse that value or that voltage, to calculate the square of that value, etc. One of its most important applications, however, consists of a magnetic-coated dynamic memory tape or track presenting three states: a state of positive magnetization, a state of demagnetization and a state of negative magnetization.

As illustrated in FIGS. 7 and 8 one form of dynamic memory device of this type includes a base 30 on which a drum 31 with a magnetizable coating 32 is rotatably mounted. Suitable power means 33 are provided for rotating drum 31 relative to fixed reading heads 34a, 34b and 34c also mounted on base 30. The reading heads are of known construction and may be made up of a magnetic circuit or split core 35 which carries magnetic flux and a coil or winding 36 having terminals 37 and 38 as shown in the enlargement of FIG. 9. The surfaces or tracks 32 a, 32b and 320 of magnetic coating situated under the reading heads 34 may have the infonnation signals-h 0 and recorded thereon, respectively, in the form of positive dipoles N-S, demagnetized zones O-0 O-O and negative dipoles S-N. When a memory track is moved in the direction of the arrow F in FIG. 9, relative to the reading head 34, a

signal voltage v is generated at terminals 37, 38 which c when.

plotted against time t as the abscissa, according to curves vl (FIG. 10 B) in response to the passage of a positive dipole zone N-S, according to curve v2 (FIG. 10D) in' response to the passage of a demagnetized zone 0-0 and according to curve v3 (FIG. 10 F) in response to the passage of a negative dipole zone S-N.

In order to distinguish a signalO or a' series of O'signals indicating absence of information on the memory track, it is necessary to provide a reference signal vr (FIG. 10 A) which can be read by one of the reading heads. This may by accomplished as illustrated in FIG. 11 by associating reading head 34c with a memory track 32c on which a series of positive dipole zones N-S have been recorded. This results in the generation of a voltage signal vr at terminals 370, 380.

One can now obtain the product of the reference signal vr and the unknown signals recorded on anothertrack, for example track 320, by connecting terminals 37 c, 380 to points P and B of a multiplier circuit L,M embodying the invention, preferably also through an amplifier Tof known construction.

According to whether the unknown recorded signals are positive valueless (0) or negative the potential V at output terminal S varies with time according to curves S1, S2 or S3 FIGS. 10 C, 10 E and 10 G), respectively, thus restoring the signals 0 and One may, if desired, record a series of negative dipoles S-N on track 320 in order to obtain output signals V having signs contrary to those recorded on track 32a, for example (Fig. 1 1

For recording signals of the above nature on a magnetic track 32 of the coated drum 31, one may make use of a novel combination consisting of a comparator circuit W and acommutator circuit Ml (FIG. 12) which are disclosed in the aforementioned French Pat. No. 1,478,391 and in the US. Pat. No. 3,41 1,019 respectively.

In the form illustrated comparison circuit W contains-two transistors T7 and T8 of the same type, for example NPN, having collector, emitter and base terminals. The collector terminals of transistors T7 and T8 are connected by a conductor 50 and resistances R12 and R13, respectively, to asourceof I voltage V,,. The base of transistor T7 and the emitter of transistor T8 are connected through resistors R14 and R15 respectively, to a signal input terminal 51. The base of transistor T8 and the emitter of transistor T7 are connected through resistors R17 and R16, respectively, to a terminal 52. Connections are made at points 53 and 54 to connect the collectors of transistors T7 and T8 to the base terminals of two type PNP transistors T10 and T9, respectively. The collector terminals of transistors T9 and T10 are connected to a junction 55 through resistors R18 and R19, respectively, and the emitter terminals thereof are connected to a junction 56 which is also connected through a resistance R20 to conductor 50 and hence to the source of voltage V.

Another transistor T11. of the same type as transistors T9 and T10 has its emitter terminal connected to junction 56 and its collector terminal connected through a resistor R21 to a junction 55 which isin turn connected to the mass or ground. The base terminal of transistor T11 is connected through a resistor'R22 to supply line 50 and through resistors R23 and R24 to junctions 57 and 58, respectively, and thence to the collectors of transistors T9 and T10.

The: commutator circuit; M1 comprises a NPN-type transistorTlZ andaPNP-y type transistor T13. An input terminal 59 is connected to the collector terminal of transistor T11 and through resistors R25 and R26 to the base electrodes of transistors T12 and T13, respectively. The collector terminal of transistor T12 is connected to aterminal 61, and the emitter terminal of transistor T13 is connected to junction 58 and hence to the collector terminal of transistor T10. The emitter terminal of transistor T12 and the collector terminal of transistor T13 are connected. directly to an output terminal 60 and thence to one terminal 37d (or 38d) of the winding of a recording head'-34d,-the construction of which is similar to the reading heads described above.

In the operation of the recording circuitry of FIG. 12, some signal voltages V,, V, and v representing the values 0 and are supplied attenninal 51.while the points 52 and 38d (or 37d) are carried to voltage V,,, the point 55 is carried to voltage V;.and the terminal 61 is carried to a high frequency (about kilocycles) alternating current voltage having a mean value equal to V If the signalinput at terminal 51 has a voltage of V, greater than V the voltage of the base tenninal of transistor T7 becomes greater than the voltage of its emitter terminal, the voltage on the base'terminal of transistor T8 becoming in turn less than that on its emitter tenninal. The result. is that transistor T8 is blocked, transistor T7 is conductive, and the potential of point 53 and of the base terminal of transistor T10 is lowered.

Asthis transistor becomes conductive while transistors T9 andTll remain blocked, the potential V, of point 58 and of the emitter of transistor T13 becomes simultaneously greater than the'voltage V,, at point 59 and on the base of transistor T13 which is saturated. The potential of terminal 37d of the writing or recording head is then equal to V, for recording a positive signal on themagnetic memory track 32.

When the signal applied to terminal 51 is a voltage Vless than V,, the voltage of the base of transistor T8 becomes greater than the voltage of its emitter, while the voltage of the base of transistor T7 becomes less than that of its emitter. The

\ result is that transistor T7 is blocked, transistor T8 becomes conductive, and thepotential at point 54 and the base of transistor T9 islowered. Since transistors T10 and T11 remain blocked as doalso-the:transistors T12 and T13, the voltage on terminal 3.72i-of the recording head is equal to V, for recording a negative signal on the track 32.

Finally when thesignal applied to terminal 51 is a voltage V,, both transistors T7v and T8 are blocked as are also transistors T9 and T10. On the contrary, T11 becomes conductive by virtue of the voltage divider bridge consisting of resistors'R22, R23 and R24. The result is that transistor T12 becomes saturated, and the high frequency signal applied to input tenninal 61. is applied to recording head terminal 37d. The magnetic track below the recording head is thereby demagnetized to record a 0 signal.

It will be notedthat resistances R22, R23 and R24, thanks to which the base of transistor T11 is placed under voltage, allow for establishing equal thresholds,fields or paths for the voltages applied to terminal 51, according to the invention.

The specificembodiment of the above described comparator circuit as shown in FIG. 13 with the specific component values shown indicates, for example, whether the voltage V applied to the input terminal 51 is equal to V, i

E or less than V the 6 6 being, for example,- equal to 4 volts. 7

greater than V lvalue 6 I claim:

1. An electronic multiplier circuit for effecting the product of two numbers A and B represented by means of electrical voltages indicative of positive values, negative values and no value which voltages may be supply phase and control phase voltages for a two-phase motor or supply voltages for the rotor and stator of a synchronous motor, said circuit comprising a device capable of delivering on two output electrodes voltages indicative of numbers A and A when a voltage indicativeof the number A is supplied to an input electrode of said device, and a commutator, having an output terminal, a control terminal for receiving a voltage indicative of number B and two input terminals connected to said output electrodes of said device, said commutator being adapted, if B is positive, to connect its output terminal with said output electrode deliveringthe voltage indicative of the number A and, if B is negative, to connect said output terminal with said output electrode delivering the voltage indicative of the number A, and finally, if B has no value, to connect both said output electrodes of said device to said output terminal of said commuta- 01.

2. A circuit as defined in claim 1 wherein said device comprises first and second transistors of inverse types each having an en emitter, a collector and a base, the emitter of the first transistor and the collector of the second transistor being connected in parallel to one terminal of a source of electrical current through a common resistance, the collector of the first transistor and the emitter of the second transistor being connected to said output electrodes of said device and through separate equal parallel resistance to the other terminal of said source, the base of one .of the transistors being connected to said input electrode of the device, and the base of the other of the transistors being connected to a point in the circuit having a predetermined potential.

3. A circuit as defined in claim 2 in which said point'of predetermined potential is between tow two polarization resistances connected in series across said source.

4. A circuit as defined in claim 3 wherein said common resistance and th the polarization resistance connected to the same terminal of said source each has an ohmic value equal to one half the ohmic value of each of said parallel resistances and of the other polarization resistance,

5. A circuit as defined in claim 2 comprising a resistance connected between said input electrode of the device and the base of said one transistor.

6. A circuit as defined in claim 1 wherein said commutator lector, an emitter and a base, said bases being connected 10. A circuit as defined in claim 8 wherein the vibration emitters are Hertzian radiating oscillators and said receivers are transistors having base terminals equipped with antennae.

11. A circuit as defined in claim 8 wherein the vibration emitters are electric vibrators and vibration receivers are carbon granule microphones.

through'separate equal parallel resistors to said commutator control terminal, and the emitter of one transistor and the collector of the other a transistor being connected through separate equal parallel resistors to the commutator output terminal.

7. A circuit as defined in claim 6 wherein the collector of said said one transistor and the emitter of said othertransistor are connected to said commutator input terminals.

8. A circuit as defined in claim -1 wherein said commutator comprises two vibration emitters coupled to the control terminal thereof and two vibration receivers, the electrical characteristics of which vary in response to the vibrations of the corresponding vibration emitters, each of said vibration receivers being connected in series with a resistance between one of the input terminals of the commutator and the output terminal of the commutator, the resistances in series with said receivers being of equal ohmic value.

9. A circuit as defined in claim 8 wherein said vibration emitters are nonpolarized gaseous discharge tubes and said vibration receivers are photoelectric resistances.

12. A circuit as defined in claim 3 wherein said commutator comprises two vibration emitters connected in series across said source of electrical current and having a center tap connected to said control terminal, and two vibration receivers the electrical characteristics of which vary in response to vibrations of the corresponding vibration emitters, each of said receivers being connected in series with a resistance between a respective commutator input terminal and commutator output terminal.

13. A circuit as defined in claim 1 wherein the commutator output terminal is connected to the bases of two transistors of inverse type embodying emitters and collectors respectively connected to an output terminal and across a source ofelectrical current, said two last-named transistors constituting a socalled push-pull amplifier.

14. The combination of a circuit as defined in claim 1 with a two two-phase motor having a control 'phase winding, the energization of which is responsive to the voltage on the commutator output terminal.

15. The combination of a circuit as defined in claim 1 with a two-phase motor having a control phase winding connected across a source of electrical current in series with said device and commutator.

16. The combination of a circuit as defined in claim 1 with a self-synchronous motor having a rotor winding connected between a source of electrical current and the commutator control terminal and a stator winding connected between a source of electrical current and said input electrode of the device.

17. Electrical apparatus comprising a source of electrical energy, circuit means connected across said source comprising first and second resistors, a first solid state conduction control device interposed between said resistors in series therewith, a third resistor and a second solid a state conduction control device interposed between said first and third resistors in series therewith, each said conduction control device havingan input terminal connected to said first resistor, an output terminal connected to a respective one of said second and third resistors and a control terminal, a source of variable signal voltage, means including said source of signal voltage for connecting the control terminal of one of said conduction control devices to a source of voltage of predetermined constant amplitude, and means for connecting the control terminal of the other of said conduction control devices to a source of voltage of predetermined constant amplitude.

18 Apparatus as defined in claim 17 wherein the parameters of the components of the apparatus are so related that the voltages at the output terminal of one of said conduction control devices will correspond with said signal voltage indicative of preselected values of a ternary number and the voltage at the output terminal of the other of said devices will be indicative ofithe value of the complement of said said number.

19. Electrical apparatus as defined in claim 17 wherein said second and third resistors are of substantially equal ohmic value.

20. Electrical apparatus as defined in claim 17 wherein said conduction control devices are transistors having emitter, collector and base terminals.

21. Electrical apparatus as defined in claim 20 wherein the emitter of one transistor and the collector of the other transistor constitute the input terminals, the collector of said constitute the control terminals thereof.

' one transistor is of PNP type.

22. Electrical apparatus as defined in claim 21 wherein said 23. Elec "can apparatus as defined in claim 22 wherein said other transistor is of NPN type.

respectively to the outoutput terminals of said circuit means, an output terminal and a signal input terminal a sourr e of variable signal voltage, means including the latter for connecting said first-named source of voltage of predetermined constant amplitude to said commutator signal input terminal, and solid state conduction control means responsive to voltage applied to said commutator signal input terminal for selectively connecting said commutator output terminal to either or both o f said two commutator input terminals.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent 3 151+LH78O Dated December 1, 1970 Inventor) Pierre Jorgensen It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Front page, ABSTRACT, line 1, "electric" should read electronic Column 1 line 18, cancel "2". Column 2 line 2, cancel "her"; line 66 cancel "and and insert I will be seen that Column i, line 1, "v V 1 shoul and B2- read V and V line '72, cancel "resi stance,

R1 R2 Column line 3, cancel "an; line 5, cancel "t"; line 10, I! H z should read h lines +l and +5 the capital letter after "and" 2 should be the numeral O line 58 "C08" should read cos line 62, "to sin2" should read and to sin line 6 after "filter inse: Q Column 5, line 29, cancel "0" and insert varies line +6, after "terminals" insert 37a,38a

(Fig. ll) to terminals A and P preferably through a suitable amplifier T of known construction and connecting terminals Column 6, line 16, cancel "-y". Column '7, line cancel "tow"; line +7, cancel "th". Column 8, line 23, cancel "two"; line +1, cancel "a", third occurrence.

Signed and sealed this 23rd day of March 1971 Attes-t:

EDWARD M.FLETCHER, R- WILLIAM E. SCHUYLER, JF Attesting Officer Commissioner of Patents 

